freescale qo riq? com munications platforms are the next-generation evolution of our leading powerquicc ? communications processors. built using high-performance power architecture ? cores, freescale qoriq platforms enable a new era of networking innovation where the reliability, security and quality of service for every connection matters. qoriq p2020 and P2010 communications processors the qoriq p2 platform series, which includes the p2020 (dual-core processor) and P2010 (single-core processor) communications processors, delivers high single-threaded performance per watt for a wide variety of applications in the networking, telecom, military and industrial markets. the series delivers dual- and single-core frequencies up to 1.2 ghz on a 45 nm technology low-power platform. the qoriq p2020 and P2010 dual- and single- core products are pin-compatible with the qoriq p1 platform products, offering four interchangeable cost-effective solutions. scaling from a single-core processor at 533 mhz (p1011) to a dual-core processor at 1.2 ghz (p2020), the two qoriq platforms together deliver an impressive 4.5x aggregate frequency range within the same pinout. the devices in these two series are software-compatible, sharing the e500 power architecture core and peripherals, as well as being fully software compatible with the existing powerquicc processors. this enables customers to create a product with multiple performance points from a single board design. the p2020 and p1020 dual-core processors support symmetric and asymmetric multi-processing, enabling customers to scale performance through either thread-level or application- level parallelism. the p2020 and P2010 communications processors both have an advanced set of features for ease of use. the optional integrated security engine supports the cryptographic algorithms commonly used in ipsec, ssl, 3gpp and other networking and wireless security protocols. the 64-bit memory controller offers future-proofing against memory technology migration with support for both ddr2 and ddr3. it also supports error correction codes, a baseline requirement for any high-reliability system. other memory types such as flash are supported through the 16-bit local bus, usb, sd/mmc and spi. the P2010 and p2020 processors integrate a rich set of interfaces, including serdes, gigabit ethernet, pci express ? , rapidio ? technology and usb. the three 10/100/1000 ethernet ports support advanced packet parsing, flow control and quality of service features, as well as ieee ? 1588 time stamping. qoriq? communications platforms p2 series P2010 and p2020 single- and dual-core communications processors qoriq? p2020 and 2010 block diagram 32 kb l1 i-cache power architecture ? e500 core 32 kb l1 d-cache 512 kb l2 cache 32 kb l1 i-cache power architecture e500 core 32 kb l1 d-cache ddr2/ddr3 sdram controller not on P2010 coherency module system bus 2 x serial rapidio ? 2 x serial rapidio ? 2 x 4-ch. dma 2 x 4-ch. dma 3 x pci express ? on-chip network on-chip network 4-lane serdes security acceleration (optional) xor interrupt control, sd/mmc, spi, usb 2.0/ulpi 3 x gigabit ethernet enhanced local bus controller (elbc) cores
target applications the P2010 and p2020 processors serve in a wide range of applications, especially those that have tight thermal constraints. with an available junction temperature range of -40c to +125c, the devices can be used in power-sensitive defense, aerospace and industrial applications, and less-protected outdoor environments. they enable various combinations of data plane and control plane workloads in networking and telecom applications that require higher performance but want to avoid the complexity of partitioning the application across many cores. the devices primary target applications are networking and telecom linecards. the p2 devices, with their low power budget and high single-threaded performance, are uniquely well-suited for control plane applications. control plane applications tend to be more sequential in nature and thus lose scaling efficiency with increasing number of threads or cores. the p2 series, with its low power, efficient dual-issue out-of-order e500 core, power architecture technology, and high 1.2 ghz frequency, offers a level of single- threaded performance that is a perfect fit for control plane applications. the networking linecard requires an optimal combination of good performance to manage a large amount of control plane traffic balanced against low power and cost. with convenient i/o, flexible core configurations and an on-board security block, the P2010 and p2020 processors are well-suited for this application, which involves controlling asics, managing exceptions and routing table maintenance. the P2010 and p2020 processors are also well-suited for long term evolution (lte) and wimax channel card applications. with dual-core performance in single-core power budgets, the p2 series facilitates the flattening of the wireless network hierarchy. the dual serial rapidio interfaces allow direct connection to the dsps (such as freescales msc8156 dsp) that implement layer 1 processing as well as redundant backplane connections. technical specifications ? dual (p2020) or single (P2010) high-performance power architecture e500 cores 36-bit physical addressing double-precision floating-point support 32 kb l1 instruction cache and 32 kb l1 data cache for each core 800 mhz to 1.2 ghz clock frequency ? 512 kb l2 cache with ecc. also configurable as sram and stashing memory. ? three 10/100/1000 mbps enhanced three- speed ethernet controllers (etsecs) tcp/ip acceleration and classification capabilities ieee 1588 support lossless flow control r/g/mii, r/tbi, sgmii fifo interfaces ? high-speed interfaces supporting various multiplexing options four serdes to 3.125 ghz multiplexed across controllers three pci express interfaces two serial rapidio interfaces two sgmii interfaces ? high-speed usb controller (usb 2.0) host and device support enhanced host controller interface (ehci) ulpi interface to phy ? enhanced secure digital host controller (sd/mmc) ? serial peripheral interface ? integrated security engine (sec 3.1) (optional) crypto algorithm support includes 3des, aes, rsa/ecc, md5/sha, arc4, kasumi, snow 3g and fips deterministic rng single pass encryption/message authentication for common security protocols (ipsec, ssl, srtp, wimax) xor acceleration ? 64-bit ddr2/ddr3 sdram memory controller with ecc support ? programmable interrupt controller (pic) compliant with openpic standard ? two four-channel dma controllers ? two i 2 c controllers, duart, timers ? enhanced local bus controller (elbc) ? 16 general-purpose i/o signals ? pac kage: 689-pin wirebond power-bga (tepbga2) freescale, qoriq, corenet and the freescale logo are trademarks or registered trademarks of freescale semiconductor, inc. in the u.s. and other countries. all other product or service names are the property of their respective owners. the power architecture and power.org word marks and the power and power.org logos and related marks are trademarks and service marks licensed by power.org. ? freescale semiconductor, inc. 2009. document number: qp20xxfs rev 3 learn more: for current information about freescale products and documentation, please visit www.freescale.com/qoriq . qoriq? platform device cores top core frequency l2 size ddr 2/3 support ge ports serdes pci express ? serial rapidio ? tdm p1 p1011 1 800 mhz 256 kb 32-bit with ecc 3 4 2 n/a yes p1 p1020 2 800 mhz 256 kb 32-bit with ecc 3 4 2 n/a yes p2 P2010 1 1200 mhz 512 kb 64-bit with ecc 3 4 3 2 n/a p2 p2020 2 1200 mhz 512 kb 64-bit with ecc 3 4 3 2 n/a
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